As one of semiconductor device wafers, there is an SOI (Silicon On Insulator) wafer having a silicon layer (which may be referred to as an SOI layer hereinafter) formed on a silicon oxide film as an insulator film. This SOI wafer has characteristics such as a small parasitic capacitance or a high radiation-proof capability since the SOI layer in a substrate surface layer portion that functions as a device fabrication region is electrically separated from the inside of the substrate by, e.g., a buried insulator layer (a buried oxide film layer (a BOX layer)). Therefore, effects such as a high-speed/low-power-consumption operation, prevention of a software error, and others can be expected, and this wafer appears promising as a substrate for a high-performance semiconductor device.
As a typical method for manufacturing this SOI wafer, there is a wafer bonding method. The wafer bonding method is a method of forming a thermal oxide film on, e.g., a surface of at least one of a bond wafer and a base wafer consisting of a silicon single crystal, then closely attaching the two wafers to each other through the formed thermal oxide film, performing a bonding heat treatment to increase a bonding force, and thereafter reducing a film thickness of one wafer (a wafer on which the SOI layer is formed (which will be referred to as the bond wafer hereinafter)) by, e.g., grinding or mirror polishing, thereby manufacturing an SOI wafer.
In case of the thus manufactured SOI wafer, a portion called a polishing sag or a chamfered portion where a thickness is slightly small is present in a peripheral portion of the two bonded wafers, and bonding is not effected in such a portion, or this portion remains as a unbonded portion having a weak bonding force. When a film thickness is reduced by, e.g., grinding while such an unbonded portion is present, the unbonded portion is partially delaminated during the film thickness reducing process. Therefore, the bond wafer having a reduced film thickness has a diameter smaller than that of the base wafer that serves as a base, and small irregularities are continuously formed in the peripheral portion.
When such an SOI wafer is put in a device process, the remaining unbonded portion is delaminated during the device process, particles are produced, and a device yield is lowered.
Therefore, the remaining unbonded portion is removed in advance by attaching a masking tape to expose the peripheral portion on the upper surface of the thinned bond wafer and performing etching. The outer peripheral region where the unbonded portion is removed and the base wafer is exposed in this manner is called a terrace portion.
On the other hand, as a method for reducing a film thickness of a bond wafer, there is a method of previously forming an ion implanted layer having hydrogen ions or the like implanted therein on a bond wafer before bonding, bonding the bond wafer to a base wafer, and then delaminating the bond wafer at the ion implanted layer to reduce a film thickness of the bond wafer besides the above-described method based on grinding/polishing. This so-called ion implantation delamination method can reduce a film thickness of an SOI layer to be fabricated and greatly improve film thickness uniformity, and hence this method has been actively utilized.
According to this ion implantation delamination method, likewise, a polishing sag portion becomes an unbonded portion, and an SOI layer is not transferred to the polishing sag portion after delamination, thus resulting in a terrace portion where a base wafer is exposed.
In recent years, as a wafer that is very useful for a bipolar device or a power device, an SOI wafer having a relatively large thickness in which an SOI layer has a film thickness of several μm to several-ten μm has been greatly expected.
However, when manufacturing a high-quality SOI wafer that a film thickness of an SOI layer must be several μm and a thickness tolerance must be approximately ±0.1 μm, the method for reducing a film thickness of a bond wafer by grinding/polishing can obtain radial uniformity of at most approximately ±0.3 μm only with respect to a target film thickness even though a highly accurate polishing technique is utilized, irregularities in film thickness of the SOI layer are considerable, and the film thickness uniformity has a limit.
Thus, as a method for realizing this configuration, there is, e.g., Japanese Patent Application Laid-open No. 2000-30995. In this Japanese Patent Application Laid-open No. 2000-30995, a thin SOI layer is formed by the ion implantation delamination method that can relatively easily obtain the film thickness uniformity of SOI layer that is ±0.01 μm or below, and epitaxial growth is carried out on a surface of this SOI layer, thereby increasing a film thickness of the SOI layer.
In this case, however, when an oxide film is previously formed on a base wafer and wafers are then bonded to fabricate an SOI wafer while considering warpage of the SOI wafer, since the oxide film on a peripheral terrace portion (the unbonded portion) of the SOI wafer is exposed, carrying out the epitaxial growth on an entire surface of the SOI layer in this state causes polysilicon to grow on the oxide film on the terrace portion, resulting in a factor of, e.g., particle contamination in subsequent processes.
In general, the SOI wafer is immersed in an HF aqueous solution to remove the oxide film on the terrace portion and then the epitaxial growth is carried out in order to prevent this polysilicon from growing, but a film thickness of the oxide film on a back surface is also reduced when the oxide film on the back surface that avoids warpage remains on the base wafer, and hence the warpage of the SOI wafer to be manufactured increases.
To solve such a problem, it can be considered that the oxide film on the terrace portion alone is completely removed and then the epitaxial growth is carried out, or the oxide film on the terrace portion alone is removed after the epitaxial growth to simultaneously remove the polysilicon formed on the oxide film on the terrace portion by, e.g., a method for performing HF spin cleaning like Japanese Patent Application Laid-open No. 2006-270039 in order to prevent the oxide film on the back surface that avoids the warpage of the SOI wafer from being reduced beyond necessity, but a BOX layer below the periphery of the SOI layer is considerably corroded and an unstable overhand structure is provided when the oxide film on the terrace portion is completely removed in this manner, which results in a problem of a particle generation source.